Technical Field
Embodiments described herein relate to the field of integrated circuit design and more particularly, to methods for reducing the load on the bitlines of a ROM bitcell array.
Description of the Related Art
The semiconductor industry aims to manufacture integrated circuits with higher and higher densities of semiconductor devices on a smaller chip area to achieve greater functionality and to reduce manufacturing costs. This desire for large scale integration has led to a continued shrinking of circuit dimensions and device features. However, as technological advances enable smaller integrated circuit features, spacing between devices and layers is reduced, thereby increasing capacitance. The increased capacitance results in degraded performance, increased current leakage, and decreased reliability. The impact will be more significant if there is a large load on a long running wire.
In view of the above, methods and mechanisms for reducing the load on integrated circuit wires are desired.